Field Programmable Gate Array (FPGAs) - Application Notes
 | AT40K Series Configuration (33 pages, updated 1/99)
Configuration is the process by which a design is loaded into an AT40K series FPGA. AT40K series devices are SRAM based and can be configured any number of times. | |||
| |  | AT00 Series Configuration (21 pages, updated 9/99)
This document suggests guidelines for device congifuration and describes each of the configuration modes in detail. | ||
| | Recommended Design Methods (9 pages, updated 9/99)
Described here are a series of guidelines for designing with AT00 Series FPGAs. | |||
| | Implementing Cache Logic with FPGAs (5 pages, updated 9/99)
This Application Note describes our enabling technology to make adaptive hardware possible for electronics systems. | |||
| | Data Acquisition Systems Using Cache Logic FPGAs (5 pages, updated 9/99)
"This Application Note describes our enabling technology to make adaptive hardware possible for Data Acquisition, Logic Analyzer, and other instrumentation products." | |||
| | "High-Speed, Loadable 16-Bit Binary Counter" (5 pages, updated 9/99)
"The AT00 Series FPGA lets the designer implement a fast synchronous, loadable 16-bit binary counter that operates at 70 MHz on and off chip under the worst commercial operating conditions." | |||
| | "Compact, Loadable 16- and 32-Bit Binary Counters" (4 pages, updated 9/99)
"The AT00 Series architecture accommodates dense, synchronous, loadable binary counters." | |||
| | 16-Bit Up/Down Counter Shift Register (4 pages, updated 9/99)
"The AT00 Series FPGA lets the designer implement a synchronous, 16-bit Up/Down Counter/Shift Register that operates at 22 MHz under the worst commercial operating conditions." | |||
| | 9-Bit Programmable Terminal Counter (5 pages, updated 9/99)
"The AT00 Series FPGA lets the designer implement a synchronous, programmable 9-bit terminal counters optimized for speed or layout area." | |||
| | 16-Bit Carry-Select Adder (3 pages, updated 9/99)
A carry-select adder implemented in the AT00 achieves speeds 40% faster by performing additions in parallel and reducing the maximum carry path. | |||
| | Ripple-Carry Adders (3 pages, updated 9/99)
"With a NAND and an XOR available simultaneously in a single cell, the AT00 architecture is ideally suited for implementing arithmetic operations, including parallel adders." | |||
| | Barrel Shifter (3 pages, updated 9/99)
"The AT00 Series FPGA allows the designer to implement fast compact 8-bit barrel shifters, and modular shifters that can be easily sized for specific needs." | |||
| | 24-Bit Magnitude Comparator with 50-ns Response (5 pages, updated 9/99)
The AT00 Series FPGA lets the designer implement a magnitude camparator that can compare two 24-bit binary integers in 50 ns. | |||
| | "16-Bit, Four-To-One Multiplexer with 15-ns Delay" (3 pages, updated 9/99)
The AT00 Series FPGA lets the designer implement a 16-bit four-to-one multiplexer with a 15 ns delay from the select control to the most significant output bit. | |||
| | 8-Bit S-P/P-S Corner-Bender Data Converter (5 pages, updated 9/99)
"Using the AT05 device, two S-P/P-S corner-bender circuits were implemented: one optimized for area and power consumption, the other for speed and expandability." | |||
| | 16-Word by 8-Bit FIFO (5 pages, updated 9/99)
"The AT00 Series FPGA lets the designer implement a synchronous, first-in, first-out (FIFO) register buffer with a word width and depth tailored to specific design needs." | |||
| | IEEE 1149.1-1990 Standard Test Access Port & Boundry-Scan (8 pages, updated 9/99)
"For system or board diagnostics, AT00 Series devices can be programmed with the 1149.1 standard test logic and then reprogrammed for normal operation when the diagnostics are complete." | |||
| | Digital Frequency/Phase Comparator (DFPC) (4 pages, updated 9/99)
The AT00 Series FPGA lets the designer implement a digital frequency/phase comparator (DFPC) that interfaces to a voltage controller oscillator (VCO). | |||
| | Configuration Compression Algorithm (2 pages, updated 9/99)
The AT00 Series FPGAs are SRAM-based and can be reconfigured to perform different applications in a system. | |||
| | Modeling Device Power Consumption (3 pages, updated 9/99)
This Application Note provides a simple method for modeling the active and static power consumption of a AT05 design. | |||
| | Edge Detection in AT00 FPGAs (5 pages, updated 9/97)
In the Application Note we present a reference design of a fully pipelined bit-parallel edge detection circuit that utilizes only pipelined adders and fits into one AT10 FPGA. | |||
| | 3x3 Convolver with Run-time Reconfigurable Vector Multiplier in Atmel AT00 FPGAs (9 pages, updated 8/99)
In this Application Note we present an efficient single-chip FPGA implementation of a bit-parallel 3x3 symmetric convolver that features run-time software-configurable convolver coefficients (taps). | |||
| | DSP Acceleration Using Reconfigurable Coprocessor FPGA (6 pages, updated 9/99)
"Digital signal processors (DSPs), like their FPGA counterparts, are proliferating into a broad range of compute intensive applications, including telecommunications, networking, instrumentation and computers." | |||
| | Implementing Bit-Serial Digital Filters (9 pages, updated 9/97)
This Application Note describes the implementation of digital filters in the Atmel AT00 Series FPGAs. | |||
| | Symmetrical 8-tap FIR Filter Macro (FIR8S) (3 pages, updated 8/97)
This Application Note details implementation of a 8-Tap FIR Filter Macro in the AT00 Series FPGAs. | |||
| | Symmetrical 16-tap FIR Filter Macro (FIR16S) (2 pages, updated 8/97)
This Application Note details implementation of a 16-Tap FIR Filter Macro in the AT00 Series FPGAs. | |||
| | Symmetrical 24-tap FIR Filter Macro (FIR24S) (2 pages, updated 8/97)
This Application Note details implementation of a 24-Tap FIR Filter Macro in the AT00 Series FPGAs. | |||
| | Symmetrical 32-tap FIR Filter Macro (FIR32S) (2 pages, updated 8/97)
This Application Note details implementation of a 32-Tap FIR Filter Macro in the AT00 Series FPGAs. | |||
| | Standard 8-Tap FIR Filter Macro (FIR8) (3 pages, updated 9/97)
This Application Note details implementation of a standard 8-Tap FIR Filter Macro in the AT00 Series FPGAs. | |||
| | Second-Order IIR Digital Filter Macro (IIR) (3 pages, updated 9/97)
This Application Note details implementation of a second-order IIR Digital Filter Macro in the AT00 Series FPGAs. | |||
| |  FPGA-based FIR Filter Using Bit-Serial Digital Signal Processing (10 pages, updated 9/99)
This Application Note describes the implementation of an FIR Filter with variable coefficients that fits in a singel AT02 FPGA. | |||
| | HDLPlanner® Design Development Environment for HDL-based FPGA Designs (8 pages, updated 10/99)
"HDLPlanner solves the addition design cycle problem by providing an environment for creating technology independent HDL designs, which guaranteed to product performance delivering layouts." | |||
